Language_Version: VHDL-93
Classification: Language Modeling Enhancement or Deficiency
Summary: Remove LINKAGE mode ports
Relevant_LRM_Sections: 1.1.1.2
Description_of_Problem: Linkage mode ports are useless and needlessly clutter the language and complicate tool implementations.
Proposed_Resolution: Remove LINKAGE mode from the LRM
Related_Issues:
Key_Words_and_Phrases: LINKAGE, MODE, PORT
Authors_Name: Stephen Bailey
Authors_Phone_Number: 303-581-2467
Authors_Fax_Number: 303-581-9972
Authors_Email_Address: sbailey@veribest.com
Authors_Affiliation: VeriBest Inc.
Authors_Address1: 6101 Lookout Rd., Suite A
Authors_Address2:
Authors_Address3: Boulder, CO 80301
irmail.pl: Submit Issue Report
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